As known in the art, a plurality of integrated circuit (IC) chips are formed on a semiconductor wafer by performing semiconductor processing including lithography, etch, ion implant and thin film processes. Following formation of the IC chips, the wafer is sawed for singulation of the chips. The vacant wafer spaces between the IC chips used for sawing the wafer are referred to as scribe line areas.
To assess electrical properties of elements (e.g., MOS transistors) constituting an IC chip, a predetermined pattern of measuring elements or test elements (so-called test modules (TMs)) are generally formed in the scribe line areas of the wafer. The TM is electrically tested by an automatic test system including a probe card, prober system and measurement apparatus, and can be performed after an early metal level (e.g., first metal) and/or after completion of wafer processing, for determining whether circuit elements are suitably formed (e.g., proper threshold voltage and breakdown voltage) in the IC circuit chips formed on the wafer.
Since the TMs are formed using the same process as the process for forming the elements in the IC chips, testing electrical properties of the devices in the TM is identical to testing electrical properties of the elements formed in the IC chips. Accordingly, the properties of the IC chips can be generally be accurately deduced by testing the TM(s).
Process technologies, particularly analog and mixed signal technologies, have significant constraints on both wafer scribe area and scribe test time given the extensive component count and electrical tests needed to properly characterize. A standard 1×16 (1 pin wide, 16 pins long) TM can accommodate up to 4 MOS devices, with 1 pin used for each of the MOS Sources, Gates, Drains, and Substrate/Body terminals. In one arrangement, sharing Gate, Source and Substrate pins globally (i.e. between all devices) in the TM is known, with the Drain pin used to select the particular MOS in the TM for testing. This approach for a standard 1×16 TM increases the number of MOS devices in the TM to 12, so that the number of placed MOS devices approaches the number of test pins.
In another TM arrangement, multiplex circuitry is used to raise the number of placed devices in the TM per pin, to generally achieve more placed devices than number of test pins. However, multiplex circuitry requires dedicated test pins for its implementation (e.g., for circuitry for biasing and indexing) and also has loading effects on the devices during test. It would be desirable to reduce the area of the TM, increase the number of devices in the TM, reduce the number of TMs needed to measure performance, and decrease the test time, without the need for additional circuitry (e.g., such as multiplex circuitry).